The present invention is applicable to buried bit line memory cells such as DRAM, SRAM, ROM, PROM, EEPROM, PAL, PLA, etc., memory cells. The invention is illustrated herein for DRAM cells.
A DRAM cell typically comprises a MOS transistor and a capacitor. An example of such a DRAM cell is shown in FIG. 1. The DRAM cell 10 of FIG. 1 comprises the MOSFET 12 and the capacitor 14. A word line is connected to the gate of the MOSFET 14. A bit line is connected to the source of the MOSFET 12. The capacitor 14 is connected to the drain of the MOSFET 12. The state of the DRAM cell 10 is determined by whether or not the capacitor 14 is holding a charge.
The DRAM cell is read by using the bit line to determine whether or not a charge is stored in the capacitor. The DRAM cell is written by using the bit line to add or remove charge from the capacitor. However, the cell can only be read or written when the cell is addressed (i.e. activated) by the word line.
With the continuous advancement of DRAM technology, the chip area used for one DRAM cell is getting smaller. For example, in the fabrication of memory cell arrays, it is often desirable to minimize the cell width and the spacing between bit lines in order to increase the capacity of a given size array. The source and drain regions of a MOSFET of a memory cell formed by prior art photolithographic techniques are shown in simplified form in FIG. 2. The cell has a source bit line region 2 and a drain region 4 formed in a substrate 6. The minimum value of a source or drain region width x, or a channel distance c within a substrate 6, is nominally equal to the smallest width m of masking element 8, as limited by photolithographic technology, e.g. 0.65 .mu.m. Moreover, the minimum value of channel distance c is further limited by punch-through considerations, between n.sup.+ region 2 and n.sup.+ region 4.
It is an object of the present invention to reduce cell width x to a value less than mask width m. It is a further object of the present invention to improve the punch-through characteristics of channel c, without increasing the size of mask width m.